Accelerated N-channel dynamic register
US7348806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Sep 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.