Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains
US7348813B1 · kind B1 · utility
4Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Dec 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.