Apparatus and methods for adjusting performance of programmable logic devices
US7348827B2 · kind B2 · utility
44Cited by
45References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2004 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | May 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.