Method and apparatus for DC offset cancellation in amplifiers
US7348839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Aug 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45618
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.