Adaptive digital pre-distortion system
US7348844B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Sep 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2623
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An adaptive Digital Pre-distortion System and a method for correcting especially power amplifier memory effects. In particular, the invention relates to an electronic circuit, for amplifying an input signal, comprising: a clipping unit for generating a signal, having a reduced peak-to-average power ratio by clipping the input signal; a pre-distorter for generating a pre-distorted signal, defined by an pre-distortion algorithm which is based on the amplifier model function; a representation unit for representing the amplifier model function; a non-linear processing unit, in particular a power amplifier, for generating a processed signal, in particular by amplifying said received pre-distorted signal; a time delay unit for compensating the processing time for the pre-distorted signal generating the delayed pre-distorted signal; and a time delay cascade for delaying the said delayed pre-distorted signal, at the integer sample clocks generating the signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.