Automatic biasing and protection circuit for field effect transistor (FET) devices
US7348854B1 · kind B1 · utility
30Cited by
3References
35Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Jul 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor biasing circuit is shown that utilizes a negative feedback loop control circuit to set the gate bias voltage in the output transistors of a power amplifier. This control circuit has a current sensor in series with the drain of the transistor, the current sensor output in turn feeding a dc signal into a dc amplifier, and the output of the dc amplifier driving a gate bias integrator which forms a dc control loop for maintaining the bias point. The output transistor is protected from excessive temperature and/or excessive power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.