Passive component having stacked dielectric layers
US7348868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2004 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Jul 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P1/20345
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A passive component comprising one input electrode layer constituting an input terminal, one output electrode layer constituting an output terminal, and four shield electrode layers constituting shield terminals, all formed in the lowermost dielectric layer by via holes. The input electrode layer is connected electrically with an input-side resonance electrode, in the vicinity of the second side face of a dielectric substrate, through a via hole made in the fourth through sixth dielectric layers and an input tap electrode. The output electrode layer is connected electrically with an output-side resonance electrode, in the vicinity of the third side face of the dielectric substrate, through a via hole made in the fourth through sixth dielectric layers and an output tap electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.