Reconfigurable mixed-signal VLSI implementation of distributed arithmetic
US7348909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Aug 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.