Non-volatile memory device
US7349235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | May 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.