Semiconductor memory device
US7349249B2 · kind B2 · utility
33Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Sep 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.