Semiconductor memory device
US7349267B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. In an active period, the source bias control circuits perform potential control so that one or more of the source lines selected by row predecoders which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.