Packet receiver with the influence of jitter and packet losses reduced before a buffer becomes idle due to data delays and packet receiving method using the same
US7349330B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/32
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet receiver includes a packet memory circuit for temporarily storing received packets in a FIFO (First-In First-Out) fashion in the form of a queue. A read start threshold setting circuit sets, with respect to the length of the queue, a read start threshold at which the received packets should begin to be read out. A read comparing circuit determines whether or not the length of the queue has reached the read start threshold, and outputs a read command signal in accordance with the result of decision. In response to the read command signal, a read control circuit causes the received packets to be read out of the packet memory circuit. The packet receiver reduces the influence of the jitter of a communication network on speech quality. Also, the packet receiver reduces the influence of delays of packets by executing discard processing with the queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.