Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector
US7349514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2004 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | May 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer, for integration in a low voltage digital CMOS process, controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls a center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop. The analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This parametric difference allows two separate control inputs to the VCO, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.