Cache coherency protocol including generic transient states
US7350032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2004 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | May 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.