Method and apparatus for placement and routing cells on integrated circuit chips
US7350173B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2003 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Apr 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell. Timing is analyzed using a route of the wire connecting the first cell and the second cell to select a second path from the set of paths before a cell is placed on the second path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.