Cascode, cascode circuit and method for vertical integration of two bipolar transistors into a cascode arrangement
US7352051B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Aug 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/643
Abstract
A cascode of a high-frequency circuit, includes a first transistor having a first base semiconductor region, a first collector semiconductor region and a first emitter semiconductor region, and a second transistor having a second base semiconductor region, a second collector semiconductor region and a second emitter semiconductor region. The first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor are geometrically arranged on top with respect to a wafer surface, while the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor are geometrically arranged on the bottom with respect to the wafer surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.