Semiconductor devices having amorphous silicon-carbon dielectric and conducting layers
US7352065B2 · kind B2 · utility
4Cited by
9References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Sep 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device having a plurality of layers, depositing a first layer comprising a medium-k dielectric barrier layer on one of the plurality of layers, depositing a second layer comprising a low-k dielectric layer on the first layer, and depositing a third layer comprising a medium-k dielectric barrier on the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.