System and method for clock detection with glitch rejection
US7352214B2 · kind B2 · utility
8Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Feb 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.