Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling
US7352229B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2006 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Jul 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0294
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.