Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique
US7352247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2007 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Aug 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7206
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.