Oscillator circuit with tuneable signal delay means
US7352253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Jan 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit further comprises a signal delay means (120, 220, 320, 420) which is arranged in series with the oscillating element and feeds the output signal back to the oscillating element. The delay means is (120, 220, 320, 420) tuneable with respect to the delay it provides. The oscillating element can be an amplifier or a VCO, and the delay means can be a Delay Locked Loop or a tuneable delay line, depending on the embodiment of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.