Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits
US7352610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Apr 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.