Method for operating a data storage apparatus employing passive matrix addressing
US7352612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Nov 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation. The data storage cells of the apparatus are provided in two or more electrically separated segments such that each segment comprises a separate physical address space for the apparatus. In an addressing operation the data are directed to a segment that is selected based on information on prior and/or scheduled applications of active voltage pu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.