Electronic memory with binary storage elements
US7352619B2 · kind B2 · utility
4Cited by
17References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Feb 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.