NOR flash memory device with multi level cell and read method thereof
US7352623B2 · kind B2 · utility
2Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NOR flash memory device includes a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage, and a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.