Memory device
US7352645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.