Frame mapping scheduler with compressed mapping table
US7352752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Oct 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/623
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a mapping table. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and a particular one of the transmission elements. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry to identify the particular transmission element. The mapping table is stored in a compressed format in memory circuitry associated with the scheduling circuitry. More specifically, the mapping table is stored as a compressed mapping table in which a particular entry identifies one of a plurality of stored values which is processed to determine a corresponding uncompressed mapping table entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.