Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support
US7353368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2000 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Nov 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.