LDPC architecture
US7353444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Jul 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.