Method of fabricating CMOS transistor and CMOS transistor fabricated thereby
US7354835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Jun 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.