Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate
US7355214B2 · kind B2 · utility
3Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | May 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor, and a gate electrode of a n-channel type field effect transistor on the silicon layer which has the strain effect through a gate insulating film. The sources and drains of p- and n-type diffusion layers are then formed in the silicon layer having the strain effect, on both sides of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.