Patent · US Active

Dynamic bias circuit for use with a stacked device arrangement

US7355375B2 · kind B2 · utility

4Cited by
5References
30Claims
0Family size

Assignee

Inventor

Key dates

Filing dateSep 30, 2005
Grant dateApr 8, 2008
Priority date—
Expiry dateSep 26, 2026

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG05F3/205
  • WIPO fieldControl
  • WIPO sectorInstruments

Abstract

A regulator circuit includes a first transistor coupled to a supply voltage and a second transistor coupled between the first transistor and an output node. The regulator circuit also includes a dynamic bias circuit that may selectively provide a bias voltage to a gate of the second transistor. During a first mode such as a low power mode, for example, the bias circuit may provide the bias voltage at a fixed percentage of the supply voltage as the supply voltage varies. In addition, during a second mode such as a high power mode, for example, the bias circuit may provide the bias voltage at a fixed offset from the supply voltage as the supply voltage varies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.