Patent · US Active

Physical layers

US7355467B2 · kind B2 · utility

4Cited by

5References

4Claims

0Family size

Assignee

Tundra Semiconductor Corporation · CA

Inventors

Steven M. Waldstein · Scarborough, US
Maurice Richard · Gorham, US
Alexander Alexeyev · Gorham, US
David Reynolds · Castle Rock, US

Key dates

Filing date	Aug 14, 2006
Grant date	Apr 8, 2008
Priority date	—
Expiry date	Aug 14, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/0013
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.