Methods and arrangements for reducing partial discharges on printed circuit boards
US7355832B2 · kind B2 · utility
0Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Jun 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10977
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and arrangements for reducing partial discharges on a printed circuit board are provided. A method of reducing partial discharge in a printed circuit board includes providing a conducting surface coupled to a component under at least one of electrical and thermal stress, wherein the conducting surface is a metallic plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.