Column redundancy reuse in memory devices
US7355909B2 · kind B2 · utility
4Cited by
4References
12Claims
0Family size
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Inventor
Key dates
| Filing date | Jul 12, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Oct 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column redundancy structure is also arranged into an addressable first redundancy column and an addressable second redundancy column. A first column array which is found to be defective is replaced by mapping its address to the first redundancy column. In a similar manner, a second column array which is found to be defective is replaced by mapping its address to the second redundancy column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.