Hybrid data recovery system
US7356095B2 · kind B2 · utility
5Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data recovery circuit, multiple slicer outputs of incoming data for each data bit, e.g., one or more slicer outputs taken at or near the center of the eye and one or more slicer outputs taken at or near the leading edge and/or trailing edge of the eye, are processed in a manner that reduces the bit-error rate relative to the prior art. The data recovery circuit may be combined with state-of-the-art clock recovery circuits to yield improved clock and data recovery (CDR) circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.