Variable fixed multipliers using memory blocks
US7356554B1 · kind B1 · utility
7Cited by
1References
37Claims
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Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Oct 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.