Configurable width buffered module having a bypass circuit
US7356639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | May 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. The configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module. The configurable width buffer device includes a multiplexer/demultiplexer circuit coupled to the entry pin and the internal channel for accessing the memory device. A bypass circuit is coupled to the entry pin and the exit pin in order to allow information to be transferred through the memory module to another coupled memory module in the memory system by way of an external channel. In an alternate embodiment of the present invention, two bypass circuits are coupled to a pair of entry and exit pins. In an embodiment of the present invention, a memory system may include at least four interfaces, or sockets, for respective memory modules having config…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.