Warp processor for dynamic hardware/software partitioning
US7356672B2 · kind B2 · utility
6Cited by
8References
30Claims
0Family size
Assignee
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Key dates
| Filing date | May 28, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Mar 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A warp processor includes a microprocessor, profiler, dynamic partitioning module, and warp configurable logic architecture. The warp processor initially executes a binary for an application entirely on the microprocessor, the profiler monitors the execution of the binary to detect its critical code regions, and the dynamic partitioning module partitions the binary into critical and non-critical code regions, re-implements the critical code regions in the configurable logic, and then transforms the binary so that it accesses the configurable logic rather than execute the critical code regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.