Method and user interface for debugging an electronic system
US7356786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Jan 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.