Architecture for face-to-face bonding between substrate and multiple daughter chips
US7358601B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Sep 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of second integrated circuit dice have logical function circuits disposed thereon and further have a second array of face-to-face bonding structures disposed on a first face thereof. The second array of face-to-face bonding structures of each member of the family mates with a different portion of the first array of face-to-face bonding structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.