Inverting dynamic register with data-dependent hold time reduction mechanism
US7358775B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | May 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and kill signals comprises a hold time, and where the hold time is shortened when the logic function evaluates to the first state. The latching logic is responsive to the clock and kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of the kill signal, and otherwise presents a tri-state condition to said output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.