Read and/or write detection system for an asynchronous memory array
US7359281B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides an asynchronous electronic circuit that has an asynchronous memory circuit where the memory cells are arranged in columns and rows. The asynchronous circuit includes a read completion detection circuit and a write completion detection circuit that determines an end of the read cycle or the write cycle for a word byte of information. Upon completion of the read or write cycle an acknowledge signal is generated from the read completion detection circuit or the write completion detection circuit. The read and/or write acknowledge signal is used as a control signal to advance the electronic circuit to the next subsequent step in a process. The invention further provides a method for detecting the end of a read and/or write cycle issuing an acknowledge signal that may be used to provide control to an asynchronous electronic circuit to advance to the next step in a sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.