Apparatus and method for recovering clock signal from burst mode signal
US7359461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
There are provided an apparatus and method for recovering a clock signal from a burst mode signal. A first delay delays an input data signal for half of a time period of the input data signal, and produces a first delay signal. An XOR gate adds the input data signal and the first delay signal provided from the first delay, and provides an inverted signal of the added signal. An OR gate adds an output signal of the XOR gate and a second delay signal, and provides the added signal as a recovered clock signal. A second delay delays the added signal provided from the OR gate for an integer multiple of a time period of the input data signal, and produces the second delay signal that is provided to the OR gate. The frequency of the recovered clock signal is not limited by any delay in the gate elements due to a phase transition of the input data signal occurring when every other packet is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.