Apparatus for synchronizing clock and data between two domains having unknown but coherent phase
US7359468B2 · kind B2 · utility
3Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2002 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jun 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse. A synchronizer jitter lockout circuit inputs the edge pulse and the sampling clock and outputs a data sampling enable signal which never coincides with a data transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.