Patent · US Expired

Signal delaying device and method for dynamic delaying of a digitally sampled signal

US7359469B2 · kind B2 · utility

0Cited by

3References

11Claims

0Family size

Assignee

Rohde & Schwarz GmbH & Co. KG · DE

Inventors

Stephan Neumann · Munich, DE
Kurt Schmidt · Grafing, DE
Markus Freidhof · Kirchseeon, DE

Key dates

Filing date	Jan 20, 2004
Grant date	Apr 15, 2008
Priority date	—
Expiry date	Feb 3, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/13
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A signal delaying device (1) for the dynamic delaying of a digitally sampled input signal comprises a memory element (2) and a series-connected interpolation element (3). According to the invention, a register (30), which can be connected to the output side of the interpolation element (3), is arranged in parallel to the memory element (2) for intermediate storage of at least one sampled value (Sin(k)) of the input signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.