Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces
US7360031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Apr 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space. If the cache snoop identifies a modified cache line, a copy of that cache line is returned to the I/O agent; otherwise, the copy of the data retrieved from the shared memory space is returned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.