Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory
US7360115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Mar 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having a processor that has halted execution. Virtual to physical address translation data from the target computer is transferred to the host computer. The host computer utilizes the virtual to physical address translation data to access data pointed by virtual memory addresses that were used by the target computer, and then debugs a fault by accessing the data by reading the physical memory address on the host computer. After the virtual to physical memory address translation data have been acquired, they can be cached at the host computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.