Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
US7360135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Aug 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self test provides results, i.e. pass or fail, of an array to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.