Verification of the design of an integrated circuit background
US7360138B2 · kind B2 · utility
1Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | Feb 23, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jul 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is created for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.